Minimal RISC-V SoC

This webpage documents my learning journey while working on my Minimal RISC-V SoC project, which I started in 2024. Aside from that, it also contains a formal datasheet, notes on microarchitecture choices, my testing infrastructure and more. My hope is that having a project guide from start to end will help others dust their FPGAs off and get to work designing cool hardware.

Note

This documentation is also available to download as a PDF.

Contents

• Motivation
• Specification
  • Naming conventions
• RISC-V CPU
• FPGAs
• Testing
• Project log
  • Instruction support
  • TODO
• Tools
  • Open source ASIC/FPGA tools
  • Codespell
  • Extra steps
  • Custom scripts
  • Editor
• Resources

Use the table of contents above to navigate to the next section or use the sidebar to read at your own will!